COMPUTER FUNDAMENTALS AND DIGITAL SYSTEMS-B.C.A-OCT-2019
SAINTGITS
COLLEGE OF APPLIED SCIENCES
MODEL INTERNAL ASSESSMENT EXAMINATION, OCTOBER2019
Department of Computer Application (BCA) , Semester I
Fundamentals
of Digital Principles
Total : 80 marks Time:3Hours
Section
A
Answer Scheme
1.
a. 0010 b.0111
2.
Storage area for storing n bit of information
3.
A. 00010100 B. 00011000
4.
5.∑(1,4,5,6)
6. Output depends not only on
present input but also on past output.
7.
- 7. A + (A.B) = A (OR Absorption Law)
- A(A +
B) = A (AND
Absorption Law)
8. The World
Wide Web (WWW), commonly known as the Web, is
an information
system where documents and
other web resources are identified by Uniform
Resource Locators (URLs,
such as https://www.example.com/), which may be interlinked
by hypertext, and are accessible over the Internet.
9.
The Domain Name System (DNS)
is the phonebook of the Internet. Humans access information online through
domain names, like nytimes.com or espn.com. Web browsers interact through
Internet Protocol (IP) addresses. DNS translates domain names to IP addresses
so browsers can load Internet resources.
10.In digital logic, a don't-care term
for a function is an input-sequence (a series of bits) for which the function
output does not matter.
11. In JK flip flop as long as
clock is high for the input conditions J&K equals to the output changes or
complements its output from 1–>0 and 0–>1. This is called toggling output
or uncontrolled changing or racing condition.
12. RAM—Volatile memory
ROM---Non
Volatile
13. 
Truth table
14. A decoder is a combinational logic circuit which is used to
change the code into a set of signals. It is the reverse process of an encoder.
A decoder circuit takes multiple inputs and gives multiple outputs. A decoder
circuit takes binary data of ‘n’ inputs into ‘2^n’ unique output. In addition
to input pins, the decoder has a enable pin. This enables the pin when negated,
makes the circuit inactive. in this article, we discuss 3 to 8 line Decoder and
Multiplexer.
15. Decimal
Octal
Hexadecimal
Binary(Explain all)
16. a. 5.875 b. 661 c.4797 d. 98 e.76476
17. F = Y′ + W′Z′ + XZ′. Draw diagram
18.
Explain each parts
19. Flatbed plotters.
Drum Plotters. ...
Pinch Roller Plotters. ...
Electrostatic Plotters. ...
Inkjet Plotters. ...
Cutting Plotters(write any five)
20. Simple Batch System.
Multiprogramming Batch System.
Multiprocessor System.
Desktop System.
Distributed Operating System.
Clustered System.
Realtime Operating System.
Handheld System.(write any five)
21.
Master
Slave JK Flip Flop
Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and
if clk=1 for a long period of time, then Q output will toggle as long as CLK is
high, which makes the output of the flip-flop unstable or uncertain. This
problem is called race around condition in J-K flip-flop. This problem (Race
Around Condition) can be avoided by ensuring that the clock input is at logic
“1” only for a very short time. This introduced the concept of Master Slave JK flip flop.
Master Slave JK flip flop –
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop.
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop.
In addition to these two flip-flops, the
circuit also includes an inverter.
The inverter is connected to clock pulse in such a way that the inverted clock
pulse is given to the slave flip-flop. In other words if CP=0 for a master
flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop
then it becomes 0 for slave flip flop.
Working
of a master slave flip flop –
1. When the clock pulse goes to 1, the slave is isolated; J and
K inputs may affect the state of the system. The slave flip-flop is isolated
until the CP goes to 0. When the CP goes back to 0, information is passed from
the master flip-flop to the slave and output is obtained.
2. Firstly the master flip flop is positive level triggered and
the slave flip flop is negative level triggered, so the master responds before
the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the
K input of the slave and the clock forces the slave to reset, thus the slave
copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the
J input of the slave and the Negative transition of the clock sets the slave,
copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the
clock and thus the slave toggles on the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains
unchanged.
22. definition, Explanation,truth
table, diagram
23.
Dot-Matrix printer.
Laser Printer.
Ink-Jet Printer.
Color Thermal Printer.
3D Printer.
(Explanation needed)
24. Explain in details
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