UG-S3 Micro-processor & PC Hardware, First Internal Examination, August 2024

 

Section A

Answer any 5 questions. Each question carries 2 marks.

1. Define Program Counter and Stack Pointer

Program Counter (PC):

The Program Counter is a register that holds the address of the next instruction to be executed in the sequence.

Stack Pointer (SP):

The Stack Pointer is a register that points to the top of the current stack in memory.

2. What are the Types of BUS in Microprocessor

Address Bus:

The Address Bus carries the address of the memory location or I/O device that the CPU wants to access.

Data Bus:

The Data Bus transfers actual data between the CPU, memory, and peripheral devices.

Control Bus:

The Control Bus carries control signals, such as read/write commands and interrupt requests, to coordinate and manage the activities of the CPU and other components.

3. What is an Interrupt? List Out the Types.

Hardware Interrupts: Generated by external hardware devices (e.g., keyboards, mice).

Software Interrupts: Triggered by software instructions or programs (e.g., system calls).

Maskable Interrupts: Can be enabled or disabled by the CPU.

Non-Maskable Interrupts (NMI): Cannot be disabled and are used for critical events.

4. What are General Purpose Registers?

General purpose registers are used by the CPU to store temporary data and intermediate results during program execution. They are versatile and can be utilized for various operations, including arithmetic, data transfer, and addressing.

5. List Out the Different Generations of Microprocessors

First Generation (1971-1972): Characterized by 4-bit microprocessors like the Intel 4004, which had limited processing power.

Second Generation (1973-1978): Featured 8-bit microprocessors like the Intel 8008 and 8080, offering improved performance.

Third Generation (1978-1980): Included 16-bit microprocessors such as the Intel 8085 and 8086, which were more powerful and efficient.

Fourth Generation (1981-1995): Introduced 32-bit microprocessors like the Intel 80386 and 80486, with multitasking capabilities.

Fifth Generation (1995-Present): Encompasses 64-bit microprocessors, including the Intel Pentium and Core series, with advanced features like multi-core processing.

6. List Out the Status Flags in 8085 MP

Carry Flag (CY): Indicates a carry out of the most significant bit in an arithmetic operation, used for multi-byte arithmetic.

Parity Flag (P): Shows if the number of 1s in the result is even (P=1) or odd (P=0), used for error checking.

Auxiliary Carry Flag (AC): Signals a carry out from the lower nibble (4 bits) in arithmetic operations, useful for BCD arithmetic.

Zero Flag (Z): Set if the result of an operation is zero, used to determine equality or to loop until a condition is met.

Sign Flag (S): Indicates the sign of the result (1 for negative, 0 for positive), used in signed arithmetic operations                     

(5 x 2 =10 Marks)

Section B

Answer any 3 questions. Each question carries 5 marks.

7. Define the timing diagram of 8085 for memory read and write.

Explain with neat diagram Memory Read Timing Diagram:

• T1 Cycle:
• Address Bus (A15-A8, AD7-AD0): The CPU places the address of the memory location on the address bus.
• ALE (Address Latch Enable): Goes high to indicate that the address bus contains a valid address.
• IO/M: Low, indicating a memory operation.
• RD (Read): Goes low, signaling that the CPU intends to read data from the memory.
• T2 Cycle:
• Address Bus: Continues to hold the address.
• Data Bus (D7-D0): Memory places the data on the data bus.
• RD: Remains low during this cycle.
• T3 Cycle:
• Data Bus: CPU reads the data from the data bus.
• RD: Goes high, signaling the end of the read operation.
• Address Bus: The next address can be placed on the bus.

Memory Write Timing Diagram:

• T1 Cycle:
• Address Bus (A15-A8, AD7-AD0): The CPU places the address of the memory location on the address bus.
• ALE: Goes high to indicate that the address bus contains a valid address.
• IO/M: Low, indicating a memory operation.
• WR (Write): Initially high.
• T2 Cycle:
• Address Bus: Continues to hold the address.
• Data Bus (D7-D0): CPU places the data to be written on the data bus.
• WR: Goes low, signaling that the CPU intends to write data to the memory.
• T3 Cycle:
• Data Bus: Continues to hold the data.
• WR: Remains low.
• T4 Cycle:
• WR: Goes high, signaling the end of the write operation.
• Data Bus: Data is written into the memory, and the bus can be freed for the next operation

8.  Explain the instruction cycle

The Instruction Cycle is the sequence of steps that the CPU follows to execute an instruction. It consists of three main phases:

1. Fetch Cycle:
• The CPU fetches the instruction from memory. This involves placing the address of the instruction on the address bus, activating the read control signal, and reading the instruction from the data bus into the instruction register.
2. Decode Cycle:
• The CPU decodes the fetched instruction to determine the operation to be performed. This involves interpreting the opcode and, if necessary, identifying the addressing mode and operands.
3. Execute Cycle:
• The CPU performs the operation specified by the instruction. This can involve arithmetic or logical operations, data transfer, or control operations. The result is then stored in the appropriate register or memory location.

9. Explain the Intel 8085 instruction set

The Intel 8085 instruction set is divided into several categories:

1. Data Transfer Instructions:
• MOV: Copy data from source to destination (e.g., MOV A, B).
• MVI: Move immediate data to a register or memory (e.g., MVI A, 55H).
• LXI: Load immediate data into register pair (e.g., LXI H, 2050H).
• LDA/STA: Load/Store data from/to memory (e.g., LDA 2050H, STA 3050H).
• LDAX/STAX: Load/Store data from/to memory location addressed by register pair (e.g., LDAX B).
2. Arithmetic Instructions:
• ADD: Add register or memory to accumulator (e.g., ADD B).
• ADI: Add immediate data to accumulator (e.g., ADI 10H).
• SUB: Subtract register or memory from accumulator (e.g., SUB C).
• SUI: Subtract immediate data from accumulator (e.g., SUI 05H).
• INR/DCR: Increment/Decrement register or memory (e.g., INR A, DCR B).
3. Logical Instructions:
• ANA: Logical AND register or memory with accumulator (e.g., ANA C).
• ANI: Logical AND immediate data with accumulator (e.g., ANI 0FH).
• XRA: Logical XOR register or memory with accumulator (e.g., XRA D).
• XRI: Logical XOR immediate data with accumulator (e.g., XRI 1FH).
• CMA: Complement accumulator.
4. Branching Instructions:
• JMP: Unconditional jump to address (e.g., JMP 2050H).
• JC/JNC: Jump if carry/no carry (e.g., JC 3050H).
• JZ/JNZ: Jump if zero/no zero (e.g., JZ 4050H).
• CALL/RET: Call/Return from subroutine (e.g., CALL 2050H, RET).
5. Control Instructions:
• NOP: No operation.
• HLT: Halt the processor.
• DI/EI: Disable/Enable interrupts.

10. Explain the addressing modes

Addressing modes define how the operand of an instruction is specified. The Intel 8085 microprocessor supports several addressing modes:

1. Immediate Addressing Mode:
• The operand is specified explicitly in the instruction.
• Example: MVI A, 55H (55H is the immediate data).
2. Register Addressing Mode:
• The operand is specified in a register.
• Example: MOV A, B (data in register B is moved to register A).
3. Direct Addressing Mode:
• The address of the operand is specified explicitly in the instruction.
• Example: LDA 2050H (load data from memory location 2050H into the accumulator).
4. Register Indirect Addressing Mode:
• The address of the operand is specified in a register pair.
• Example: LDAX B (load data from the memory location addressed by the BC register pair).
5. Implicit Addressing Mode:
• The operand is implied in the instruction itself.
• Example: CMA (complement the accumulator; no specific operand is mentioned).

 

               (3 x 5 = 15 Marks) 

Section C

Answer any 1 question. The question carries 15 marks

11. Explain the 8085-pin architecture with a neat Diagram

Pin Descriptions:

1. Power Supply Pins:
• Vcc (Pin 40): +5V power supply.
• Vss (Pin 20): Ground.
2. Clock Pins:
• X1, X2 (Pins 1, 2): Connect to an external clock oscillator or crystal to provide the clock frequency.
• CLK OUT (Pin 37): Output clock signal used to synchronize other peripherals.
3. Interrupt Pins:
• INTR (Pin 10): Interrupt Request, a general-purpose interrupt.
• INTA (Pin 11): Interrupt Acknowledge, indicates that the processor has acknowledged the INTR signal.
• RST7.5, RST6.5, RST5.5 (Pins 7, 8, 9): Restart interrupts, which are vectorized interrupts.
• TRAP (Pin 6): Non-maskable interrupt, highest priority.
4. DMA Pins:
• HOLD (Pin 39): Indicates that another device is requesting the use of the address and data buses.
• HLDA (Pin 38): Hold Acknowledge, indicates that the CPU has granted bus control to another device.
5. Control and Status Pins:
• RD (Pin 32): Read control signal, active low.
• WR (Pin 31): Write control signal, active low.
• ALE (Pin 30): Address Latch Enable, used to demultiplex the address-data bus.
• IO/M (Pin 34): Selects whether the operation is memory or I/O.
• S0, S1 (Pins 33, 35): Status signals, used for status indication.
• READY (Pin 35): Indicates if a peripheral is ready to transfer data.
6. Serial I/O Pins:
• SID (Pin 4): Serial Input Data.
• SOD (Pin 5): Serial Output Data.
7. Address/Data Bus:
• AD0-AD7 (Pins 12-19): Lower-order address bus multiplexed with data bus.
• A8-A15 (Pins 21-28): Higher-order address bus.

12. Explain  8085 Architecture with Diagram

The Intel 8085 microprocessor architecture is composed of various functional units that work together to execute instructions. Here's a diagram and an explanation of each component:

Functional Units:

1. Arithmetic and Logic Unit (ALU):
• Performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, XOR).
2. Registers:
• Accumulator (A): 8-bit register used in arithmetic and logical operations.
• General Purpose Registers (B, C, D, E, H, L): Used to store temporary data.
• Temporary Register: Used internally by the ALU.
• Instruction Register: Holds the current instruction.
• Program Counter (PC): Holds the address of the next instruction.
• Stack Pointer (SP): Points to the top of the stack.
3. Flags:
• Sign Flag (S): Set if the result is negative.
• Zero Flag (Z): Set if the result is zero.
• Auxiliary Carry Flag (AC): Set if there is a carry from the lower nibble.
• Parity Flag (P): Set if the number of 1s in the result is even.
• Carry Flag (CY): Set if there is a carry out of the most significant bit.
4. Instruction Decoder and Machine Cycle Encoder:
• Decodes instructions fetched into the instruction register and generates the necessary control signals.
5. Timing and Control Unit:
• Manages the operations of the microprocessor by generating timing and control signals such as RD, WR, ALE, etc.
6. Interrupt Control:
• Handles the interrupt signals, prioritizes them, and directs the CPU to the appropriate interrupt service routine.
7. Serial I/O Control:
• Manages serial data communication using SID and SOD pins.
8. Address/Data Bus:
• Address Bus: Carries the address to memory and I/O devices (A8-A15 for higher-order address, AD0-AD7 for lower-order address/data).
• Data Bus: Carries the data between the microprocessor and memory/I/O devices.

                                                                                               (1 X 15 = 15 Marks)